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at29c1024 1 megabit (64k x 16) 5-volt only cmos flash memory features fast read access time - 70 ns 5-volt-only reprogramming sector program operation single cycle reprogram (erase and program) 512 sectors (128 words/sector) internal address and data latches for 128 words internal program control and timer hardware and software data protection fast sector program cycle time - 10 ms data polling for end of program detection low power dissipation 60 ma active current 200 m a cmos standby current typical endurance > 10,000 cycles single 5v 10% supply cmos and ttl compatible inputs and outputs commercial and industrial temperature ranges description the at29c1024 is a 5-volt-only in-system flash programmable and erasable read only memory (perom). its 1 megabit of memory is organized as 65,536 words by 16 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 70 ns with power dissipation of just 330 mw. when the device is deselected, the cmos standby current is less than 200 m a. the device endurance is such that any sector can typically be written to in excess of 10,000 times. (continued) tsop top view type 1 plcc top view pin configurations pin name function a0 - a15 addresses ce chip enable oe output enable we write enable i/o0 - i/o15 data inputs/outputs nc no connect dc dont connect 0571a at29c1024 4-141
(continued) to allow for simple in-system reprogrammability, the at29c1024 does not require high input voltages for pro- gramming. five-volt-only commands determine the opera- tion of the device. reading data out of the device is similar to reading from an eprom. reprogramming the at29c1024 is performed on a sector basis; 128 words of data are loaded into the device and then simultaneously programmed. during a reprogram cycle, the address locations and 128 words of data are internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7 or i/o15. once the end of a pro- gram cycle has been detected, a new access for a read or program can begin. description (continued) device operation read: the at29c1024 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual- line control gives designers flexibility in preventing bus contention. data load: data loads are used to enter the 128 words of a sector to be programmed or the software codes for data protection. a data load is performed by applying a low pulse on the we or ce input with ce or we low (re- spectively) and oe high. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. program: the device is reprogrammed on a sector basis. if a word of data within a sector is to be changed, data for the entire sector must be loaded into the device. any word that is not loaded during the programming of its sector will be erased to read ffh. once the words of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. af- ter the first data word has been loaded into the device, successive words are entered in the same manner. each new word to be programmed must have its high to low transition on we (or ce) within 150 m s of the low to high transition of we (or ce) of the preceding word. if a high to low transition is not detected within 150 m s of the last low to high transition, the load period will end and the internal programming period will start. a7 to a15 specify the sector block diagram address. the sector address must be valid during each high to low transition of we (or ce). a0 to a6 specify the word address within the sector. the words may be loaded in any order; sequential loading is not required. once a programming operation has been initiated, and for the du- ration of t wc , a read operation will effectively be a polling operation. software data protection: a software control- led data protection feature is available on the at29c1024. once the software protection is enabled a software algo- rithm must be issued to the device before a program may be performed. the software protection feature may be en- abled or disabled by the user; when shipped from atmel, the software data protection feature is disabled. to enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. after the software data protection is en- abled the same three program commands must begin each program cycle in order for the programs to occur. all software program commands must obey the sector pro- gram timing specifications. once set, software data pro- tection will remain active unless the disable command se- quence is issued. power transitions will not reset the soft- ware data protection feature, however the software fea- ture will guard against inadvertent program cycles during power transitions. 4-142 at29c1024
temperature under bias................. -55 c to +125 c storage temperature...................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* after setting sdp, any attempt to write to the device with- out the 3-word command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effectively be a polling operation. after the software data protections 3-word command code is given, a sector of data is loaded into the device using the sector programming timing specifications. hardware data protection: hardware features protect against inadvertent programs to the at29c1024 in the following ways: (a) v cc sense if v cc is below 3.8v (typical), the program function is inhibited. (b) v cc power on delay once v cc has reached the v cc sense level, the device will automatically time out 5 ms (typical) before programming. (c) program inhibit holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. product identification: the product identifica- tion mode identifies the device and manufacturer as at- mel. it may be accessed by hardware or software opera- tion. the hardware operation mode can be used by an ex- ternal programmer to identify the correct programming al- gorithm for the atmel product. in addition, users may wish to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program op- device operation (continued) erations. in this manner, the user can have a common board design for various flash densities and, with each densitys sector size in a memory map, have the system software apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at29c1024 features data poll- ing to indicate the end of a program cycle. during a pro- gram cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7 and i/o15. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data p o l l i n g t h e at29c1024 provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 and i/o14 toggling between one and zero. once the program cycle has completed, i/o6 and i/o14 will stop toggling and valid data will be read. examining the toggle bit may begin at any time dur- ing a program cycle. optional chip erase mode: the entire device can be erased by using a 6-byte software code. please see software chip erase application note for details. at29c1024 4-143
dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 200 m a ind. 200 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc v cc active current f = 5 mhz; i out = 0 ma 60 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .45 v v oh1 output high voltage i oh = -400 m a 2.4 v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v dc and ac operating range AT29C1024-70 at29c1024-90 at29c1024-12 at29c1024-15 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c-40 c - 85 c-40 c - 85 c v cc power supply 5v 5% 5v 10% 5v 10% 5v 10% operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in 5v chip erase v il v ih v il ai standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a15 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a15 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) a0 = v il manufacturer code (4) a0 = v ih device code (4) 4. manufacturer code: 1f, device code: 25 5. see details under software product identification entry/exit. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4-144 at29c1024
ac read characteristics AT29C1024-70 at29c1024-90 at29c1024-12 at29c1024-15 symbol parameter min max min max min max min max units t acc address to output delay 70 90 120 150 ns t ce (1) ce to output delay 70 90 120 150 ns t oe (2) oe to output delay 0 35 0 45 0 60 0 70 ns t df (3, 4) ce or oe to output float 0 25 0 25 0 30 0 40 ns t oh output hold from oe, ce or address, whichever occurred first 0000 ns notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5 ns input test waveforms and measurement level output test load 70 ns 90/120/150 ns pin capacitance (f = 1 mhz, t = 25c) (1) typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v note: 1. this parameter is characterized and is not 100% tested. at29c1024 4-145
ac word load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 70 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 100 ns ac word load waveforms we controlled ce controlled 4-146 at29c1024
program cycle characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 70 ns t wlc word load cycle time 150 m s t wph write pulse width high 100 ns program cycle waveforms (1, 2, 3) notes: 1. a7 through a15 must specify the sector address during each high to low transition of we (or ce). 2. oe must be high when we and ce are both low. 3. all words that are not loaded within the sector being programmed will be indeterminate. at29c1024 4-147
software protected program cycle waveform (1, 2, 3) notes: 1. a7 through a15 must specify the same page address during each high to low transition of we (or ce) after the software code has been entered. 2. oe must be high when we and ce are both low. 3. all words that are not loaded within the sector being programmed will be indeterminate. load data to sector (128 words) (4) load data a0a0 to address 5555 load data 5555 to address 2aaa load data aaaa to address 5555 notes for software program code: 1. data format: i/o15 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write period even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 128 words of data must be loaded. enter data protect state (2) writes enabled software data protection enable algorithm (1) load data xxxx to sector (128 words) (4) load data 5555 to address 2aaa load data aaaa to address 5555 load data 8080 to address 5555 load data 5555 to address 2aaa load data aaaa to address 5555 load data 2020 to address 5555 exit data protect state (3) software data protection disable algorithm (1) 4-148 at29c1024
toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1, 2, 3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 and i/o14 may vary. 3. any address location may be used but the address should not vary. data polling waveforms at29c1024 4-149
pause 10 ms load data 9090 to address 5555 load data 5555 to address 2aaa load data aaaa to address 5555 notes for software product identification: 1. data format: i/o15 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a15 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1f device code: 25 enter product identification mode (2, 3, 5) software product identification entry (1) pause 10 ms load data f0f0 to address 5555 load data 5555 to address 2aaa load data aaaa to address 5555 exit product identification mode (4) software product identification exit (1) 4-150 at29c1024
at29c1024 4-151
ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 60 0.1 AT29C1024-70jc 44j commercial AT29C1024-70tc 48t (0 to 70 c) 60 0.3 AT29C1024-70ji 44j industrial AT29C1024-70ti 48t (-40 to 85 c) 90 60 0.1 at29c1024-90jc 44j commercial at29c1024-90tc 48t (0 to 70 c) 60 0.3 at29c1024-90ji 44j industrial at29c1024-90ti 48t (-40 to 85 c) 120 60 0.1 at29c1024-12jc 44j commercial at29c1024-12tc 48t (0 to 70 c) 60 0.3 at29c1024-12ji 44j industrial at29c1024-12ti 48t (-40 to 85 c) 150 60 0.1 at29c1024-15jc 44j commercial at29c1024-15tc 48t (0 to 70 c) 60 0.3 at29c1024-15ji 44j industrial at29c1024-15ti 48t (-40 to 85 c) package type 44j 44 lead, plastic j-leaded chip carrier (plcc) 48t 48 lead, thin small outline package (tsop) 4-152 at29c1024

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